1. Field of the Invention
The present invention relates to a semiconductor package structure and a method for manufacturing the same, and more particularly to a semiconductor package structure and a method for manufacturing the same in which an under bump metallurgy (UBM) layer is not needed to greatly reduce the manufacturing cost, and a conductive via is formed before cutting a semiconductor wafer, and the positioning structures are provided to overcome the conventional misalignment problems.
2. The Prior Arts
The conventional flip chip packaging usually connects the connection pads of a semiconductor die with a carrier board or lead frame through the metallic bumps. In a conventional method, an under bump metallurgy layer is formed between the metallic bumps and the connection pads of the semiconductor die.
Conventionally, the under bump metallurgy layer includes an adhesive layer, a barrier layer and a wetting layer sequentially stacked on the connection pad. The metallic bump can be a tin-lead bump, gold bump, copper bump, or metallic alloy bump.
As described in U.S. Pat. No. 5,508,229, a solder bump in a semiconductor device is only suitably used in an entire wafer. During the photolithography process, the alignment marks left from a previous wafer-processing step are used for the formation of an under bump metallurgy layer.
In some conventional methods, the entire wafer is not used for electroplating the metallic bump or connecting the wire lines. Instead of using the entire wafer, the wafer is cut into a plurality of semiconductor dies. Each single semiconductor die then is positioned, and allows its wiring surface affixed to an adhesive tape. Resin injection or thermal pressing is then applied to the back surface of the semiconductor die. The laser cutting or other methods then can be performed to form a blind hole to expose the connection pad of the semiconductor die on the adhesive tape. A metallic layer then can be formed by ion sputtering or chemical evaporation-plating as described in U.S. Pat. Nos. 5,353,498 and 7,067,356, or by chemical plating as described in U.S. Pat. No. 7,067,356. Alternatively, a metallic foil can be disposed on the adhesive tape, and a metallic film then can be formed in the blind hole by chemical immersion plating as described in U.S. Pat. No. 6,991,966. Subsequently, the connection pad and the outer pin can be electrically connected by a conventional method for manufacturing a printed circuit board.
In the conventional methods, the reference marks and the holes have to be firstly formed on the core board. The semiconductor die then can be positioned by using the reference marks. An encapsulating step then can be performed, and a conductive via is formed to expose the connection pad of the semiconductor die. The steps of resin injection or thermal pressing are usually performed under a high temperature condition. However, because the semiconductor die, the adhesive tape, and the core board have different coefficients of thermal expansion, the displacements may occur among these different elements during heating and cooling. As a result, the formation of the conductive via may be misaligned with the connection pad, which may affect the package quality.
Accordingly, there is a need to provide a new flip-chip packaging method without using an under bump metallurgy layer which can be applied to semiconductor wafers and/or semiconductor dies. In addition, in the new flip-chip packaging method, the semiconductor dies is not needed to be fixed on the adhesive tape before the steps of resin injection or thermal pressing so that the misalignment problem can be prevented, which is caused by the different coefficients of thermal expansion for the semiconductor die, the adhesive tape and the core board.